TMS320LF2406APZA

Product Summary

The TMS320LF2406APZA is a new member of the TMS320C24x generation of digital signal processor (DSP) controllers. It is a part of the TMS320C2000 platform of fixed-point DSPs. The TMS320LF2406APZA offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While code-compatible with the existing C24x DSP controller devices, the TMS320LF2406APZA offers increased processing performance (40 MIPS) and a higher level of peripheral integration.

Parametrics

TMS320LF2406APZA absolute maximum ratings: (1)Supply voltage range, VDD, PLLVCCA, VDDO, and VCCA: -0.3V to 4.6V; (2)VCCP range: -0.3V to 5.5V; (3)Input voltage range, VIN: -0.3V to 4.6V; (4)Output voltage range, VO LF240xA: -0.3V to 4.6V; (5)Output voltage range,VO LC240xA: -0.3V to 4.6V; (6)Input clamp current, IIK (VIN < 0 or VIN > VCC): ±20 mA; (7)Output clamp current, IOK (VO < 0 or VO > VCC): ±20 mA; (8)Operating free-air temperature ranges, TA: A version: -40℃ to 85℃; S version: -40℃ to 125℃; (9)Junction temperature range, TJ: -40℃ to 150℃; (10)Storage temperature range, Tstg: -65℃ to 150℃.

Features

TMS320LF2406APZA features: (1)High-Performance Static CMOS Technology; (2)Based on TMS320C2xx DSP CPU Core; (3)Flash (LF) and ROM (LC) Device Options; (4)On-Chip Memory; (5)Boot ROM (LF240xA Devices); (6)Up to Two Event-Manager (EV) Modules; (7)External Memory Interface; (8)Watchdog (WD) Timer Module; (9)10-Bit Analog-to-Digital Converter (ADC); (10)Controller Area Network (CAN) 2.0B Module; (11)Serial Communications Interface (SCI); (12)16-Bit Serial Peripheral Interface (SPI); (13)Phase-Locked-Loop (PLL)-Based Clock Generation; (14)Up to 40 Individually Programmable, Multiplexed General-Purpose Input/Output (GPIO) Pins; (15)Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts).

Diagrams